The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction can be any number of 16-bit parcels in length. The instruction set is designed for a wide range of uses. Notable features of the RISC-V ISA include instruction bit field locations chosen to simplify the use of multiplexers in a CPU, : 17 a design that is architecturally neutral, and most-significant bits of immediate values placed at a fixed location to speed sign extension. Its floating-point instructions use IEEE 754 floating-point. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.Īs a RISC architecture, the RISC-V ISA is a load–store architecture. Unlike most other ISA designs, RISC-V is provided under open source licenses that do not require fees to use.
RISC-V (pronounced "risk-five" : 1 where five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981 ) is an open standard instruction set architecture (ISA) based on established RISC principles.
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